Quantization noise of a sigma-delta converter is not white, but it is correlated with the input of the converter. For DC inputs, the quantization error is periodic and causes phenomena commonly referred to as idle channel tones or pattern noise. Its spectrum contains discrete tones, the frequencies and amplitudes of which depend upon the input level.
This noise may be schematically described as a sequence of pulses or a saw-tooth waveform. It has a very high peak-to-RMS (Root Mean Square) ratio, and is periodic. The periodic patterns of the quantization error may cause audible noise when sigma-delta modulators are used in audio applications.
Moreover, sigma-delta converters may generate very high-powered tones near one half the switching frequency fS/2 of the converter. Therefore, they are susceptible to being demodulated in the baseband.
To remove or attenuate the above phenomena, a technique called dithering has been devised and implemented in sigma-delta converters. The dithering technique adds a dither signal, which is a random (or pseudo-random) signal, in the sigma-delta converter loop to remove or attenuate any kind of residual periodicity in the quantization noise.
Several techniques, as recalled below, have been implemented to realize the dithering in sigma-delta converters:
a) Out-of-band sine or square waves [1] [2]. This technique is easily implemented, but requires large signals and limits the dynamic range of the converter. Moreover, the signals need to be filtered and preferably their frequency is irrational. This is relatively hard to do.
b) DC offset [3]. This technique is easily implemented, but is not very reliable because eventual DC inputs are susceptible to canceling the dither signal. Moreover, the effects of the DC offset depend from the initial conditions of the modulator.
c) Small digital noise input to the D/A converter included in any analog-to-digital sigma-delta converter [4]. This technique is easily implemented, but is not effective because the dither signal needs to be very large.
d) Small analog circuit noises injected in the feedback loop of the A/D converters [5]. This technique is easily implemented while respecting the specifications of the converter, but is not efficient because the dither signals need to be relatively large.
e) Pseudo-random noise (dither signal) input to the quantizer [6]. This technique is not easily implemented. Moreover, the dither signal needs to be correlated to the least significant bit of the quantizer. This technique is very effective if the least significant bit of the dither signal is distributed according to a rectangular probability density function, or the two least significant bits of the dither signal are distributed according to a triangular probability density function.
A block diagram of a generic second-order sigma-delta converter with addition of a dither signal, disclosed in the articles by S. Pernici et al., “A 1.8V 14b Audio Front End CODEC for Digital Cellular Phones”—Digest of ISSCC 1999 and by S. Norsworthy, R. Schreier, G. Temes, “Delta-Sigma Data Converters”—IEEE Press, is shown in FIG. 1. This architecture is used especially in high-quality audio applications, and its effectiveness depends upon the number N of bits of the digital-to-analog converter of the dither signal. Usually, a digital-to-analog converter with eight output levels (N=3) is employed.
Many references disclosing different architectures of digital-to-analog converters or sources of a dither signal, which is substantially a pseudo-random noise signal, are available in the literature. The feedback shift-register architecture depicted in FIG. 1 is probably the most used.
A sigma-delta converter including a circuit for generating a dither signal, the amplitude of which is inversely proportional to the amplitude of a signal in input to the converter, is disclosed in U.S. Pat. No. 6,462,685.
Typically, sigma-delta converters include an adder in cascade to the last integrator of the converter for adding the dither signal to a signal to be quantized by the output quantizer of the sigma-delta converter, as schematically depicted in FIG. 2 for a differential converter. Unfortunately, this approach implies a relatively large area of silicon to be occupied.
In U.S. Pat. No. 5,905,453, a sigma-delta analog-to-digital converter with a dithering circuit is disclosed. Differently from the architectures of FIGS. 1 and 2, the dither signal is added to the input of the last integrator using a dedicated array of switched capacitors. This architecture does not overcome the drawbacks of the converter of FIG. 1 because it requires additional switches for connecting the additional capacitors alternately to the input of the last integrator and to a common ground node.